In recent years, research and development projects regarding nonvolatile storage devices having memory cells structured with variable resistance elements have been moved forward. A variable resistance element is an element which has a property that a resistance value reversibly changes based on electrical signals and further can store data corresponding to the resistance value in a nonvolatile manner.
Commonly known as a nonvolatile storage device including variable resistance elements is a nonvolatile storage device including memory cells, that is, so-called 1T1R memory cells each formed by connecting in series a MOS transistor and a variable resistance element, each of which is array-arranged in a matrix at a position where a bit line intersects a word line and a source line that are arranged to be orthogonal to the bit line.
Patent Reference 1 discloses a nonvolatile storage device including 1T1R memory cells in which oxides having a perovskite-type crystal structure are used as variable resistance elements.
FIG. 28 is a schematic view of a section of a memory cell described therein.
A memory cell 1011 is structured by electrically connecting a transistor 1006 and a variable resistance element 1010 in series.
The transistor 1006 includes a source region 1002 that is the first diffusion layer region formed on a semiconductor substrate 1001, a drain region 1003 that is the second diffusion layer region, and a gate electrode 1005 formed on a gate oxide film 1004.
The variable resistance element 1010 is structured by locating, between a lower electrode 1007 and an upper electrode 1009, a variable resistance layer 1008 in which a resistance value changes based on voltage application.
The drain region 1003 and the lower electrode 1007 are electrically connected to each other.
The upper electrode 1009 is connected to a metal line that is a bit line 1012, the gate electrode 1005 is connected to a word line, and the source region 1002 is connected to a metal line that is a source line 1013.
Here, although Pr1-xCaxMnO3 (PCMO), La1-xCaxMnO3 (LCMO), and so on are disclosed as materials used for the variable resistance layer 1008, no reference to electrode materials is specifically made.
Furthermore, disclosed is a method for writing into the memory cell 1011 which can change a low resistance state into a high resistance state when a pulse voltage Vpp, a pulse voltage Vss, and a pulse voltage Vwp having a predetermined voltage magnitude are applied to the upper electrode 1009, the source region 1002, and the gate electrode, respectively, and inversely can change the high resistance state into the low resistance state when the pulse voltage Vss, the pulse voltage Vpp, and the predetermined pulse voltage Vwe are applied to the upper electrode 1009, the source region 1002, and the gate electrode, respectively.
Patent Reference 2 discloses a nonvolatile storage device including 1T1R memory cells in which variable resistance elements having a variable resistance principle different from that of the variable resistance elements in which the resistance change occurs based on the abovementioned electrical signals. This storage device is called a phase-change memory.
The phase-change memory stores data by taking advantage of a situation where a phase-change material called a chalcogenide material has a different resistance in a crystalline state and an amorphous state. Rewriting is performed by changing the state by passing a current to the phase-change material to cause the phase-change material to generate heat at near a melting point. A high resistance change (amorphization) called a reset operation is performed by control for maintaining the phase-change material at a relatively high temperature, and a low resistance change (crystallization) called a set operation is performed by control for maintaining the phase-change material at a relatively low temperature for a sufficient period.
Moreover, it is disclosed that a current required for data rewriting is different for the reset operation and the set operation, and that the, reset operation requires a relatively larger current.
FIG. 29 is a cross section of the phase-change memory disclosed in Patent Reference 2.
A memory cell 1021 is formed in a 1T1R structure using a storage unit 1022 and an NMOS transistor 1027. The NMOS transistor 1027 includes N-type diffusion layer regions 1029 and 1030 respectively corresponding to a source and a drain and a gate electrode 1031 located between the N-type diffusion layer regions.
The storage unit 1022 includes a phase change element 1024, a second metal line layer 1023 above the phase change element 1024, and a contact via 1025 and a first metal line layer 1026 below the phase change element 1024, and is connected to the N-type diffusion layer region 1029 of the NMOS transistor 1027.
The opposite-side N-type diffusion layer region 1030 of the NMOS transistor 1027 is connected to a third metal line layer 1028 via each of line layers.
Here, the second metal line layer 1023, the third metal line layer 1028, and the gate electrode 1031 of the NMOS transistor 1027 correspond to a source line, a bit line, and a word line, respectively.
Patent Reference 2 discloses adopting a mechanism for controlling source lines to a phase-change memory device and switching a direction of passing a current in a set operation and a reset operation.
A source line and a bit line are set to a predetermined high level and a low level, respectively, in the reset operation in which a relatively large current needs to be passed, and the bit line and the source line are set to the predetermined high level and the low level, respectively, in the set operation in which a relatively small current suffices.
A direction of a current in the reset operation is a direction in which a source potential of the NMOS transistor 1027 of the memory cell (in this case, corresponding to a potential of the N-type diffusion layer region 1030) is maintained at a low level almost equal to a potential of a semiconductor substrate. For this reason, since an influence of a so-called substrate bias effect of the MOS transistor is reduced, the reset operation is performed in a situation where a drive capability of the transistor is high (a large current is obtained).
On the other hand, a direction of a current in the set operation is a direction in which the source potential of the NMOS transistor 1027 of the memory cell (in this case, corresponding to a potential of the N-type diffusion layer region 1029) rises to a voltage value determined by a divided voltage relationship between an on-resistance value of the NMOS transistor 1027 and a resistance value of the phase-change element 1024. For this reason, the influence of the so-called substrate bias effect of the MOS transistor is increased, and the set operation is performed in a situation where a current flowing through the transistor is relatively kept small.
The above structure makes it easier to distinguish and supply a current having a magnitude suitable for each of the set operation and the reset operation, and allows a result of each operation to be stably obtained.
Generally, however, in order to structure a high density memory cell array, it is necessary to decrease an area of each of memory cells as much as possible, and thus it is important to decrease an area of a variable resistance element, a component of a memory cell, and an area of a transistor as much as possible.
In order to decrease the area of the transistor as much as possible, it is effective to structure a gate length L of the transistor as short as possible and a gate width W of the transistor as exact and little as possible.
This is applied to the nonvolatile storage device disclosed in Patent Reference 1.
According to Patent Reference 1, the nonvolatile storage device shown in FIG. 28 changes (increases a resistance) a low resistance state of the memory cell 1011 into a high resistance state by applying a positive voltage to the upper electrode 1009 with reference to the lower electrode 1007, that is, setting the bit line 1012 and the source line 1013 to Vpp and 0V, respectively.
Here, a potential of the source region 1002 (in this case, the source region 1002 functions as a source of the transistor 1006) that is the first diffusion layer region of the transistor 1006 is almost equal to a potential of the semiconductor substrate 1001, that is, 0V, and the substrate bias effect occurring in the transistor 1006 is minimized.
On the other hand, the nonvolatile storage device changes the high resistance state of the memory cell 1011 into the low resistance state (performs a low resistance change) by setting the bit line 1012 and the source line 1013 to 0V and Vpp, respectively.
Here, a potential of the drain region 1003 (in this case, the drain region 1003 functions as a source of the transistor 1006) that is the second diffusion layer region rises to a divided voltage between the resistance value of the variable resistance element 1010 and the on-resistance of the transistor 1006, and the substrate bias effect occurring in the transistor 1006 is greater in comparison with the case of the high resistance change.
As stated above, since performing the high resistance change with the current in the direction, in which the substrate bias effect occurring in the transistor is reduced more, does not require the driving capability of the transistor to have an unnecessary margin, the performing is rational in structuring the transistor of the memory cell with optimum dimensions, the high resistance change requiring a larger current than the low resistance change.
It is to be noted that the semiconductor device disclosed in Patent Reference 2 adopts the same concept in that the reset operation requiring the larger current is performed with the current in the direction, in which the substrate bias effect occurring in the transistor is reduced more.    Patent Reference 1: Japanese Unexamined Patent Application Publication No. 2005-25914 (FIG. 2)    Patent Reference 2: Japanese Unexamined Patent Application Publication No. 2005-267837 (FIGS. 7 and 8)